The present invention relates in general to memory circuits and, more particularly, to a non-volatile memory having a latch on each bit line.
Electrically erasable programmable read only memories (EEPROMs) are found in many applications where it is necessary to use a non-volatile memory. One such application is in the field of portable data carriers (PDC), otherwise known as smart cards. A PDC is generally made of plastic, about the size of a conventional credit card, and includes one or more semiconductor die embedded in the PDC. The semiconductor die(s) include a microprocessor, memory, and various input and output (I/O) circuitry. While a conventional credit card with a magnetic strip typically stores a few hundred bits of data, the PDC with its expanded memory can store 8K or more 8-bit bytes of data.
The additional storage capacity of the PDC vastly expands its useful applications. For example, the PDC can be used to store the user's medical history. The user presents the PDC to a health care provider who, through a PDC reader, extracts the patient's medical history, including personal data, primary care physician, health insurance, allergies, medication, past procedures, blood type, religious preference, organ donor, etc. Other applications for PDCs include banking services, identification for nationality and passport, and transportation transactions such as ticket and fare collection. For example, the PDC can be programmed to hold a monetary value. When making a purchase, the user inserts the PDC into the PDC reader and the purchase amount is automatically deducted from the stored monetary value. PDCs are applicable virtually anywhere the user needs to convey or exchange data or information.
The PDC is available to operate in contact and contactless modes. In contact mode, the PDC is inserted into the PDC reader. The PDC reader comes in direct electrical contact with terminal pads on the PDC to supply operating power and to read and write data. In contactless mode, the PDC uses radio frequency (RF) transmission circuitry. The contactless PDC is placed in the vicinity of the PDC reader and the information exchange occurs over the RF link.
The PDC generally does not contain a local power source such as a battery. The PDC receives operating power at the beginning of each transaction by the direct electrical contact, or via the RF link. The memory area on the PDC is divided between random access memory (RAM), read only memory (ROM), and EEPROM. The RAM is volatile memory and maintains temporary data used only during the time that power is supplied by the PDC reader. The ROM and EEPROM are non-volatile memory and, although can only be accessed during the time that power is supplied by the PDC reader, maintain their contents even during times of zero operating power.
The EEPROM array is arranged in a matrix of rows and columns. A row of EEPROM cells has some multiple of groups of 8 cells corresponding to a number of 8-bit bytes. For example, an 8K EEPROM array includes 256 rows with each row having 256 memory cells (32 8-bit bytes/row). Each column of memory cells includes a bit line. The bit lines must be latched to certain voltage levels during programming modes. For example, in write mode, the bit lines are latched to a high programming voltage of 20 volts. Each latch coupled to a bit line includes a data bus interface, a flipflop, and a high voltage driver to the bit line. In the prior art, the memory cell rows are typically arranged in 4 bytes groupings with 32 latches servicing one 4 byte group. The same 32 latches are routed through a selection network to service other 4 byte groups. The latch circuit, selection network, interconnections, and associated address decoders tend to be complex and consume a large area. Moreover, the latch selection limits the access capability to only 4 bytes at a time. It is desirable to access all 256 memory cells in one row at a time to reduce overall programming time without increasing the layout area.